The present invention relates to a symbol synchronous device and a frequency hopping receiver, suitable to demodulate digital-modulated signals, particularly, preferable to use in radio LAN systems.
In the spread spectrum (SS) communication technique, there are various methods including Direct Sequence (DS), Frequency Hopping (FH), DS/FH hybrid, Chirp modulation, and others.
FIG. 7 is a block diagram illustrating a conventional frequency hopping communication system. Referring to FIG. 7, the frequency hopping communication system consists of an encoder 41, a digital modulator 42, a mixer 43, a hopping pattern generator 44, a frequency synthesizer 45, a high-frequency amplifier 46, a transmission antenna 47, a receiving antenna 48, a high-frequency amplifier 49, a mixer 50, a hopping pattern generator 51, a frequency synthesizer 52, a digital demodulator 53, and a demodulator 54.
On the transmission side, the encoder 41 converts transmission data into error detectable correctable transmission data. The digital modulator 42 digital-modulates the transmission data over an intermediate frequency band. Then, the mixer 43 frequency-converts the digital-modulated signal based on the output signal of the frequency synthesizer 45. The frequency synthesizer 45 varies over time the frequency to be frequency-converted according to the hopping pattern produced by the hopping pattern generator 44, thus switching the transmission frequency channel. Thus, the digital-modulated signal is transmitted with the frequency channel according to the hopping pattern. As a result, the digital-modulated signal becomes the spread spectrum signal with a broad frequency band. The spread spectrum signal is amplified by the high-frequency amplifier 46 and then radiated from the transmission antenna 47.
On the receiving side, the spread spectrum signal is received with the receiving antenna 48 and then is amplified by the high-frequency amplifier 49. The mixer 50 inverse-spreads the amplified spread spectrum signal. The hopping pattern generator 51 generates the same hopping pattern in synchronous with the hopping pattern generator 44 on the transmission side. The frequency synthesizer 52 outputs the reference oscillation signal with the same frequency as that of the frequency synthesizer 45 on the transmission side. The frequency synthesizer 52 selectively receives the signal with the same frequency as the transmitted signal and then inverse spreads the transmitted spread spectrum signal to convert into a signal in an intermediate frequency band.
Bandpass fitlers (not shown) pass the reversed spread signal and then transmit the signal components thereof over the received frequency band in each frequency channel to the digital demodulator 53. The digital demodulator 53 performs digital demodulation corresponding to the digital demodulator on the transmission side to obtain demodulated data. The demodulator 54 subjects the demodulated data to the error and correction corresponding to the encoder 41 on the transmission side and then outputs received data.
The digital demodulator 53 multiplies the digital-modulated signal by a regenerated carrier to convert it into the baseband signal. Then, demodulated data is extracted by performing the level decision with the timing of the clock signal in synchronous with the symbol (bit) of the digital-modulated signal.
As the digital modulation method in the current mainstream are listed Frequency Shift Keying (FSK), Phase Shift keying (PSK) such as Quadrature Phase Shift keying (QPSK) and Quadrature Amplitude Modulation (QAM). In the frequency hopping communication system, the FSK digital modulation has been mainly used because of easiness of designing. However, where QPSK, QAM, or the like, performing the so-called IQ modulation, is adopted in the frequency hot communication system, the conventional carrier regenerative method and the symbol synchronous method cannot be applied without any change.
In the frequency hopping communication system, the procedure including symbol synchronization (bit synchronization), frame synchronization and data reception must be carried out every time frequency channel is changed. However, this system has a slow response characteristic to phase changes because the frequency of a carrier jitters in the initial state after a change in frequency and the reference frequency oscillator within the carrier generation circuit is based on the analog PLL system. In the digital modulation such as QPSK and QAM where the phase with respect to a carrier is modulated according to transmission data, it is difficult to regenerate the clock signal symbol-synchronized. Moreover, the symbol synchronization requires a long time. It is required to reduce the time for symbol synchronization as short as possible, in view of an improved throughput of transmission data.
The above-mentioned problem will be specifically described below by referring to the QPSK demodulation circuit in the frequency hopping system.
FIG. 8 is an IQ phase plane coordinate diagram illustrating signal points in 4-phase modulation (QPSK). Referring to FIG. 8, the X-axis represents I-phase in phase with a carrier and the Y-axis represents Q-phase perpendicular to the carrier. Before data is transmitted, the synchronous signals, the signal point in 0xc2x0 phase and the signal point in 270xc2x0 phase, for instance, are alternately repeated, so that the continuous synchronous signal where the phase changes xc2x190xc2x0 is transmitted. Thus, the carrier regeneration as well as the clock regeneration synchronized with symbols are carried out according to the synchronous signal.
FIG. 9 is a block diagram illustrating the digital demodulator of FIG. 8. Referring to FIG. 9, the digital demodulator consists of a carrier generation circuit 61, a 90xc2x0 phase shifter 2, demodulation multipliers 3 and 4, low-pass filters 5 and 6, a comparator 62, a xc2xd symbol-length delay circuit 63, an exclusive OR logic 64, decision units 65 and 66 and a decoder 67.
FIG. 10 is a diagram illustrating waveforms at various portions in the digital demodulator of FIG. 9. FIG. 10 schematically illustrates waveforms at synchronous signal reception.
Generally, carrier regeneration is carried out for the QWPSK demodulation. However, it is impossible to perfectly match the frequency of a carrier of a received digital-modulated signal with the frequency of the reference frequency oscillator on the receiving side. For that reason, the carrier regeneration is carried out based on the received signal to create a copy (replica) of a carrier. The demodulation is carried out using the replica as a reference frequency signal. First, the synchronous signal shown in FIG. 8 is received as a received signal. The carrier regeneration circuit 61 detects the carrier frequency and phase of the received signal based on the synchronous signal so that the replica of the carrier is created.
The carrier regeneration is realized by various methods. Basically, in order to achieve the frequency synchronization, a frequency-multiplied received signal is phase-compared with the output signal from the phase locked-loop (PLL). In the case of the BPSK, the frequency of the received signal is multiplied by 2. In the case of the QPSK, the frequency of the received signal is multiplied by 4.
Each of the demodulation multipliers 3 and 4 receives the created carrier replica and the oscillation signal obtained by phase-shifting the replica by 90xc2x0 with the phase shifter 2 so that the balanced demodulation can be carried out. The low-pass filter 5 extracts as a baseband component the I-phase baseband signal I, shown in FIG. 10(a), from the demodulation signal. The low-pass filter 6 extracts as a demodulation signal component the Q-phase baseband signal Q, shown in FIG. 10(b), from the demodulation signal. The decision unit 65 decides the level of the baseband signal I with the timing of the clock signal shown in FIG. 10(f). The decision unit 66 decides the level of the baseband signal Q with the timing of the clock signal shown in FIG. 10(g). Then, the decoder 67 corresponding to the location of the QPSK signal point encodes the output of the decision section and then outputs demodulation (detection) data.
The comparator 62 compares the baseband signal I or Q with a predetermined threshold and produces a binary signal with two levels (shown in FIG. 10(c)). As shown in FIG. 10(d), the xc2xd symbol-length delay circuit 63 delays the output of the comparator 62 by xc2xd of one symbol length. One symbol is a unit length in one modulation state. The exclusive OR circuit (XOR) 64 receives the output of the comparator 62 and the output of the xc2xd symbol-length delay circuit 63 and creates a clock signal with a leading timing at the center of one symbol (see FIG. 10(d)). The clock signal is symbol-synchronized with the digital-modulated signal. The level of the baseband signal I shown in FIG. 10(a) and the level of the baseband signal Q shown in FIG. 10(b) are decided with the trailing timing of the clock signal.
FIG. 11 is a block diagram illustrating the carrier regeneration circuit 61 using the Costas loop, shown in FIG. 9. Referring to FIG. 11, like numerals represent the same constituent elements as those in FIG. 9. Hence, the duplicate description will be omitted here. Numeral 71 represents a voltage-controlled oscillator (VCO). Numeral 72 represents a loop filter. Numeral 73 represents a phase error detector.
Referring to FIG. 9, it has been described that the frequency control is performed with received signals. In the Costas loop, the frequency control is substantially performed with received signals. However, specifically, the frequency control is performed with the modulated baseband signals I and Q. The phase error detector 73 calculates the baseband signals I and Q and then outputs a phase error corresponding to the phase difference between a frequency-multiplied digital-modulated signal and the carrier. The loop filter 72 smoothes the phase error and controls the oscillation frequency of the VCO 71. The VCO 71 outputs an oscillation signal in synchronous with the carrier of the digital signal and with the same frequency as that thereof.
In the carrier regeneration circuit 61, shown in FIGS. 9 and 11, the PLL carries out a carrier lock operation. After completion of locking, the output can be used as a replica of the carrier. During the locking operation, the output becomes a signal shifted in frequency and phase to the original carrier.
Since the control signal used for locking the carrier is created by a loop filter with a certain time constant, a delay occurs between the input and the output. This shift decides the response rate of the whole loop. However, when the received signals is input in a burst mode, the whole loop delay causes to take much time to complete the carrier regeneration even if the carrier regeneration starts from the burst leading. Moreover, the operation of symbol synchronization must be started after completion of carrier regeneration. In this case, the length of the preamble must be set to a quite large value for the carrier synchronization and symbol synchronization.
FIG. 12 is an explanatory diagram illustrating changes in frequency of a carrier in the frequency hopping system. In the frequency conversion on the transmission side, the carrier of a digital-modulated signal continuously varies from the frequency f1, to the current frequency f2 and converges on the vicinity of the target frequency f2 after a certain period of time. However, the carrier frequency converges on the target frequency f2 while oscillating at areas near the target frequency f2. In the frequency conversion on the receiving side, the carrier of the digital-modulated signal frequency-converted to an intermediate band converges while oscillating at areas near the intermediate frequency.
FIG. 13 is an explanatory diagram illustrating the starting portion of a transmission frame to be transmitted during one frequency hopping period.
The transmission frame is created after the carrier has been set to the target frequency. The frame format, for instance, first starts from the synchronous preamble. A frame synchronous signal and information data follow the synchronous preamble. The frame format ends with an error detection and correction code. In the preamble duration, the carrier regeneration circuit, shown in FIGS. 9 and 11, performs a phase locking operation and makes the carrier replica effective. At this time, regeneration of the clock signal symbol-synchronized becomes effective in the digital demodulator of FIG. 9.
In the frequency hopping system, the carrier of the digital-modulated signal converted to the intermediate frequency band is shifted from the intermediate frequency at the beginning of the transmission frame. The shift varies over time. The carrier regeneration circuit 61 must respond to variations in the time-varying frequency. However, since the carrier regeneration circuit 61 cannot follow and respond quickly because of the above-mentioned reasons, it is required to lengthen the synchronous preamble. Moreover, since the unit time of the frequency hopping is short, the data transmission time for synchronous preamble becomes short, so that the throughput is worsened.
In the conventional digital demodulator of FIG. 9, even if the carrier replica is locked, the duty ratio of the signal two-leveled by the comparator 62 of FIG. 9 does not become 50% because of the waveform distortion. For that reason, the delay of the xc2xd symbol-length delay circuit 63 is set improperly. As a result, the clock signal synchronized with the symbol cannot be accurately extracted.
Generally, the carrier synchronization and symbol synchronization are provided with the first received synchronous signal, the symbol-synchronized clock signal can be regenerated, without any re-synchronization, in the transmission data section following the synchronous signal. However, if there is a deviation between the frequency of the carrier of a digital-modulated signal and the reference frequency, the phase difference of the carrier to the reference frequency is enlarged or the fluctuation of the deviation over time varies the phase angle. Hence, even if the timing of the clock signal is matched with a signal point, the phase angle shifts from the phase at a predetermined signal point on the phase plane coordinate at the time the signal point is modulated with the reference frequency. As a result, demodulation cannot be performed with the timing.
In the frequency hopping system as described above, the problem is that the current technique cannot deal with regenerating the carrier at high rate, regenerating the clock symbol-synchronized at high rate, and performing demodulation following the frequency change and phase variation of a carrier.
The present invention is made to solve the above-mentioned problems.
The objective of the invention is to provide a symbol synchronous device that can maintain symbol synchronization in short time, in response to synchronous signals. Moreover, the further objective of the present invention is to provide a frequency hopping receiver using the symbol synchronous device.
The objective of the present invention is achieved by a symbol synchronous device that receives a synchronous signal at a signal point with a different phase degree to a carrier, the synchronous signal in which the phase rotational direction is reversed to the carrier, and then produces a decision timing in synchronous with a symbol of the digital-modulated signal, comprising reverse timing detection means for detecting a reverse timing at which the rotational direction of the phase angle of the digital-modulated signal is reversed; and clock signal output means for outputting a clock signal providing the decision timing in synchronous with the reverse timing.
Since the reference frequency signal does not match with the frequency of the carrier of a digital-modulated signal, the decision timing symbol synchronized can be provided even if the phase angle of the carrier of the digital-modulated signal varies with respect to the reference frequency signal. As a result, the symbol synchronization can be established in a short time. This system can shorten the length of the synchronous signal in a burst mode transmission, thus improving the throughput.
Moreover, even if there is no carrier regeneration circuit, demodulation data can be decided without being influenced by shifts and variations in frequency between the transmission device and the communication device.
In the symbol synchronous device according to the present invention, the reverse timing detection means detects the reverse timing based on a phase angle of the digital-modulated signal with respect to a reference frequency signal.
This feature allows the reverse timing to be easily detected.
In the symbol synchronous device according to the present invention, the reverse timing detection means detects the reverse timing based on a change in polarity of a differential of a phase angle of the digital-modulated signal.
Therefore, this system can detect the reverse timing without being influenced by fluctuations in frequency deviation.
In the symbol synchronous device according to the present invention, the reverse timing detection means detects the reverse timing based on a change in frequency of the digital-modulated signal.
Therefore, this system can easily detect the reverse timing.
In the symbol synchronous device according to the present invention, the clock signal output means produces a pulse signal and controls the oscillation frequency of the pulse signal according to an integration value of phase errors between the pulse signal and a reference pulse signal reversed at the reverse timing, thus outputting clock signals in synchronous with the reverse timing.
This system can generate clock signals synchronized with symbols of the signal digital-modulated in a short time, based on the reverse timing.
According to the present invention, a frequency hopping receiver comprises a symbol synchronous device that receives a synchronous signal at a signal point every time a frequency channel changes, the signal point having a different phase degree to a carrier, the synchronous signal in which the phase rotational direction is reversed to the carrier, and then produces a decision timing in synchronous with a symbol of the digital-modulated signal. The symbol synchronous device has reverse timing detection means for detecting a reverse timing at which the rotational direction of the phase angle of the digital-modulated signal is reversed; and clock signal output means for outputting a clock signal providing the decision timing in synchronous with the reverse timing.
This system has the foregoing functions and effects. Moreover, the system can start a symbol synchronous operation even in the period during which the carrier frequency does not stabilized immediately after a frequency switching operation, thus reliably performing symbol synchronization in a short time.